CPLD VGA Generator
Simply because I was told it couldn't be done — I built out a simple tile-based VGA video generator in a single 128 macrocell CPLD.
It generates VGA 640x480 resolution video at 60Hz using 8x8px tiles at 4 bit per pixel color. It supports selection of a single tileset for the entire image; or three separate tilesets, one for each horizontal third of the screen. Scrolling registers allow the image to be scrolled up to seven pixels horizontally or vertically. It still has some bugs in the CPU interface logic, but for a proof of concept I consider it a success.
It uses nearly all available logic in the CPLD, mostly for the registers used for counting pixels per line and lines per frame.
I started by laying out asynchronous logic in Logisim to see how feasible the idea would be, before transitioning to a fully synchronous design programmed in VHDL.
The project was challenging, but in the end it was easier than I expected. This simple design could easily be expanded in a larger chip (like an FPGA) to use multiple image planes, each with independent scrolling. A RAMDAC would be a great addition, since it would allow selection of 16 out of a much larger palette of colors, rather than the RGBB color I built around.